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? semiconductor components industries, llc, 1999 august, 1999 rev. 2 1 publication order number: an1048/d
by george templeton thyristor applications engineer introduction edited and updated rc networks are used to control voltage transients that could falsely turn-on a thyristor. these networks are called snubbers. the simple snubber consists of a series resistor and capacitor placed around the thyristor. these components along with the load inductance form a series crl circuit. snubber theory follows from the solution of the circuit's differential equation. many rc combinations are capable of providing accept- able performance. however, improperly used snubbers can cause unreliable circuit operation and damage to the semi- conductor device. both turn-on and turn-off protection may be necessary for reliability. sometimes the thyristor must function with a range of load values. the type of thyristors used, circuit configuration, and load characteristics are influential. snubber design involves compromises. they include cost, voltage rate, peak voltage, and turn-on stress. practi- cal solutions depend on device and circuit physics. static dv dt what is static dv dt ? static dv dt is a measure of the ability of a thyristor to retain a blocking state under the influence of a voltage transient. dv dt s device physics static dv dt turn-on is a consequence of the miller effect and regeneration (figure 1). a change in voltage across the junction capacitance induces a current through it. this cur- rent is proportional to the rate of voltage change dv dt . it triggers the device on when it becomes large enough to raise the sum of the npn and pnp transistor alphas to unity. figure 6.1. model dv dt s i a c j dv dt 1 ( n p) c eff c j 1 ( n p) i b p i j i j i k i b n i c n i 1 i 2 i c p i a two transistor model of scr c j n c j p pnp a c g c j n e p b n b p e v t g npn integrated structure k a k dv dt http://onsemi.com application note
an1048/d http://onsemi.com 2 conditions influencing dv dt s transients occurring at line crossing or when there is no initial voltage across the thyristor are worst case. the col- lector junction capacitance is greatest then because the depletion layer widens at higher voltage. small transients are incapable of charging the self- capacitance of the gate layer to its forward biased threshold voltage (figure 2). capacitance voltage divider action between the collector and gate-cathode junctions and built- in resistors that shunt current away from the cathode emit- ter are responsible for this effect. peak main terminal voltage (volts) 700 800 80 60 mac 228a10 triac t j = 110 c 600 500 400 300 200 100 120 140 160 20 100 0 180 40 static (v/ s) m dv dt figure 6.2. exponential versus peak voltage dv dt s static dv dt does not depend strongly on voltage for opera- tion below the maximum voltage and temperature rating. avalanche multiplication will increase leakage current and reduce dv dt capability if a transient is within roughly 50 volts of the actual device breakover voltage. a higher rated voltage device guarantees increased dv dt at lower voltage. this is a consequence of the exponential rat- ing method where a 400 v device rated at 50 v/ m s has a higher dv dt to 200 v than a 200 v device with an identical rating. however, the same diffusion recipe usually applies for all voltages. so actual capabilities of the product are not much different. heat increases current gain and leakage, lowering dv dt s , the gate trigger voltage and noise immunity (figure 3). figure 6.3. exponential versus temperature dv dt s static (v/ s) m dv dt 170 150 130 110 30 50 70 90 100 115 130 145 85 70 55 40 mac 228a10 v pk = 800 v t j , junction temperature ( c) 25 10 dv dt s failure mode occasional unwanted turn-on by a transient may be acceptable in a heater circuit but isn't in a fire prevention sprinkler system or for the control of a large motor. turn-on is destructive when the follow-on current amplitude or rate is excessive. if the thyristor shorts the power line or a charged capacitor, it will be damaged. static dv dt turn-on is non-destructive when series imped- ance limits the surge. the thyristor turns off after a half- cycle of conduction. high dv dt aids current spreading in the thyristor, improving its ability to withstand di dt . breakdown turn-on does not have this benefit and should be prevented. figure 6.4. exponential versus gate to mt 1 resistance dv dt s static (v/ s) m dv dt 20 100 1000 0 10 10,000 gate-mt 1 resistance (ohms) mac 228a10 800 v 110 c 40 60 80 100 120 140 r internal = 600 w
an1048/d http://onsemi.com 3 improving dv dt s static dv dt can be improved by adding an external resistor from the gate to mt1 (figure 4). the resistor provides a path for leakage and dv dt induced currents that originate in the drive circuit or the thyristor itself. non-sensitive devices (figure 5) have internal shorting resistors dispersed throughout the chip's cathode area. this design feature improves noise immunity and high tempera- ture blocking stability at the expense of increased trigger and holding current. external resistors are optional for non- sensitive scrs and triacs. they should be comparable in size to the internal shorting resistance of the device (20 to 100 ohms) to provide maximum improvement. the internal resistance of the thyristor should be measured with an ohm- meter that does not forward bias a diode junction. figure 6.5. exponential versus junction temperature dv dt s static (v/ s) m dv dt 800 1000 1200 1400 130 120 110 100 2000 2200 1800 1600 90 80 70 60 50 600 t j , junction temperature ( c) mac 15-8 v pk = 600 v sensitive gate triacs run 100 to 1000 ohms. with an external resistor, their dv dt capability remains inferior to non-sensitive devices because lateral resistance within the gate layer reduces its benefit. sensitive gate scrs (i gt 200 m a) have no built-in resistor. they should be used with an external resistor. the recommended value of the resistor is 1000 ohms. higher values reduce maximum operating temperature and dv dt s (figure 6). the capability of these parts varies by more than 100 to 1 depending on gate-cathode termination. gate-cathode resistance (ohms) figure 6.6. exponential versus gate-cathode resistance dv dt s 10 meg 1 meg 100 k 0.01 100 10 10k 0.1 1 mcr22-006 t a = 65 c 0.001 k g a 10 v static dv dt (v s) a gate-cathode capacitor (figure 7) provides a shunt path for transient currents in the same manner as the resis- tor. it also filters noise currents from the drive circuit and enhances the built-in gate-cathode capacitance voltage divider effect. the gate drive circuit needs to be able to charge the capacitor without excessive delay, but it does not need to supply continuous current as it would for a resistor that increases dv dt the same amount. however, the capacitor does not enhance static thermal stability. figure 6.7. exponential versus gate to mt 1 capacitance dv dt s static (v/ s) m dv dt gate to mt 1 capacitance ( m f) 130 120 110 100 90 80 70 60 mac 228a10 800 v 110 c 1 0.1 0.01 0.001 the maximum dv dt s improvement occurs with a short. actual improvement stops before this because of spreading resistance in the thyristor. an external capacitor of about 0.1 m f allows the maximum enhancement at a higher value of r gk .
an1048/d http://onsemi.com 4 one should keep the thyristor cool for the highest dv dt s . also devices should be tested in the application circuit at the highest possible temperature using thyristors with the lowest measured trigger current. triac commutating dv dt what is commutating dv dt ? the commutating dv dt rating applies when a triac has been conducting and attempts to turn-off with an inductive load. the current and voltage are out of phase (figure 8). the triac attempts to turn-off as the current drops below the holding value. now the line voltage is high and in the opposite polarity to the direction of conduction. successful turn-off requires the voltage across the triac to rise to the instantaneous line voltage at a rate slow enough to prevent retriggering of the device. time f i phase angle i v line g 1 2 r l time v line mt2-1 v voltage/current figure 6.8. triac inductive load turn-off dv dt c di dt c dv dt c v mt2-1 dv dt c device physics a triac functions like two scrs connected in inverse- parallel. so, a transient of either polarity turns it on. there is charge within the crystal's volume because of prior conduction (figure 9). the charge at the boundaries of the collector junction depletion layer responsible for dv dt s is also present. triacs have lower dv dt c than dv dt s because of this additional charge. the volume charge storage within the triac depends on the peak current before turn-off and its rate of zero crossing di dt c . in the classic circuit, the load impedance and line frequency determine di dt c . the rate of crossing for sinusoidal currents is given by the slope of the secant line between the 50% and 0% levels as: di dt c 6fi tm 1000 a ms where f = line frequency and i tm = maximum on-state cur- rent in the triac. turn-off depends on both the miller effect displacement current generated by dv dt across the collector capacitance and the currents resulting from internal charge storage within the volume of the device (figure 10). if the reverse recovery current resulting from both these components is high, the lateral ir drop within the triac base layer will forward bias the emitter and turn the triac on. commu- tating dv dt capability is lower when turning off from the pos- itive direction of current conduction because of device geometry. the gate is on the top of the die and obstructs current flow. recombination takes place throughout the conduction period and along the back side of the current wave as it declines to zero. turn-off capability depends on its shape. if the current amplitude is small and its zero crossing di dt c is low, there is little volume charge storage and turn-off becomes limited by dv dt s . at moderate current amplitudes, the volume charge begins to influence turn-off, requiring a larger snubber. when the current is large or has rapid zero crossing, dv dt c has little influence. commutating di dt and delay time to voltage reapplication determine whether turn- off will be successful or not (figures 11, 12). stored charge from positive conduction previously conducting side n p + lateral voltage drop reverse recovery current path gmt 1 top mt 2 nnn n nn n figure 6.9. triac structure and current flow at commutation
an1048/d http://onsemi.com 5 charge due to dv/dt figure 6.10. triac current and voltage at commutation di dt c dv dt c time i rrm volume storage charge v mt2-1 0 voltage/current main terminal voltage (v) figure 6.11. snubber delay time e t d 0 v t time e v normalized delay time figure 6.12. delay time to normalized voltage 0.2 damping factor 0.02 0.03 0.05 0.1 0.2 0.5 1 0.5 0.3 0.001 0.002 0.005 0.01 0.02 0.2 0.1 0.05 0.02 0.01 0.05 0.1 (t * = w d0 0.005 v t e r l = 0 m = 1 i rrm = 0 t d ) conditions influencing dv dt c commutating dv dt depends on charge storage and recov- ery dynamics in addition to the variables influencing static dv dt . high temperatures increase minority carrier life-time and the size of recovery currents, making turn-off more dif- ficult. loads that slow the rate of current zero-crossing aid turn-off. those with harmonic content hinder turn-off. circuit examples figure 13 shows a triac controlling an inductive load in a bridge. the inductive load has a time constant longer than the line period. this causes the load current to remain constant and the triac current to switch rapidly as the line voltage reverses. this application is notorious for causing triac turn-off difficulty because of high di dt c . figure 6.13. phase controlling a motor in a bridge l r 8.3 s + t i c r s 60 hz l s r l dc motor i di dt c high currents lead to high junction temperatures and rates of current crossing. motors can have 5 to 6 times the normal current amplitude at start-up. this increases both junction temperature and the rate of current crossing, lead- ing to turn-off problems. the line frequency causes high rates of current crossing in 400 hz applications. resonant transformer circuits are doubly periodic and have current harmonics at both the pri- mary and secondary resonance. non-sinusoidal currents can lead to turn-off difficulty even if the current amplitude is low before zero-crossing. dv dt c failure mode dv dt c failure causes a loss of phase control. temporary turn-on or total turn-off failure is possible. this can be destructive if the triac conducts asymmetrically causing a dc current component and magnetic saturation. the winding resistance limits the current. failure results because of excessive surge current and junction temperature.
an1048/d http://onsemi.com 6 improving dv dt c the same steps that improve dv dt s aid dv dt c except when stored charge dominates turn-off. steps that reduce the stored charge or soften the commutation are necessary then. larger triacs have better turn-off capability than smaller ones with a given load. the current density is lower in the larger device allowing recombination to claim a greater proportion of the internal charge. also junction temperatures are lower. triacs with high gate trigger currents have greater turn-off ability because of lower spreading resistance in the gate layer, reduced miller effect, or shorter lifetime. the rate of current crossing can be adjusted by adding a commutation softening inductor in series with the load. small high permeability asquare loopo inductors saturate causing no significant disturbance to the load current. the inductor resets as the current crosses zero introducing a large inductance into the snubber circuit at that time. this slows the current crossing and delays the reapplication of blocking voltage aiding turn-off. the commutation inductor is a circuit element that introduces time delay, as opposed to inductance, into the circuit. it will have little influence on observed dv dt at the device. the following example illustrates the improvement resulting from the addition of an inductor constructed by winding 33 turns of number 18 wire on a tape wound core (52000-1a). this core is very small having an outside diameter of 3/4 inch and a thickness of 1/8 inch. the delay time can be calculated from: t s (n a b 10 8 ) e where: t s = time delay to saturation in seconds. b = saturating flux density in gauss a = effective core cross sectional area in cm 2 n = number of turns. for the described inductor: t s (33 turns) (0.076 cm 2 ) (28000 gauss) (1 10 8 ) (175 v) 4.0 s. the saturation current of the inductor does not need to be much larger than the triac trigger current. turn-off fail- ure will result before recovery currents become greater than this value. this criterion allows sizing the inductor with the following equation: i s h s m l 0.4 n where : h s = mmf to saturate = 0.5 oersted ml = mean magnetic path length = 4.99 cm. i s (.5) (4.99) .4 33 60 ma. snubber physics undamped natural resonance 0 i lc radians second resonance determines dv dt and boosts the peak capacitor voltage when the snubber resistor is small. c and l are related to one another by w 0 2 . dv dt scales linearly with w 0 when the damping factor is held constant. a ten to one reduction in dv dt requires a 100 to 1 increase in either component. damping factor r r 2 c l the damping factor is proportional to the ratio of the circuit loss and its surge impedance. it determines the trade off between dv dt and peak voltage. damping factors between 0.01 and 1.0 are recommended. the snubber resistor damping and dv dt when r 0.5, the snubber resistor is small, and dv dt depends mostly on resonance. there is little improvement in dv dt for damping factors less than 0.3, but peak voltage and snubber discharge current increase. the voltage wave has a 1-cos ( q ) shape with overshoot and ringing. maxi- mum dv dt occurs at a time later than t = 0. there is a time delay before the voltage rise, and the peak voltage almost doubles. when r 0.5, the voltage wave is nearly exponential in shape. the maximum instantaneous dv dt occurs at t = 0. there is little time delay and moderate voltage overshoot. when r 1.0, the snubber resistor is large and dv dt depends mostly on its value. there is some overshoot even through the circuit is overdamped. high load inductance requires large snubber resistors and small snubber capacitors. low inductances imply small resistors and large capacitors.
an1048/d http://onsemi.com 7 damping and transient voltages figure 14 shows a series inductor and filter capacitor connected across the ac main line. the peak to peak voltage of a transient disturbance increases by nearly four times. also the duration of the disturbance spreads because of ringing, increasing the chance of malfunction or damage to the voltage sensitive circuit. closing a switch causes this behavior. the problem can be reduced by adding a damping resistor in series with the capacitor. v (volts) figure 6.14. undamped lc filter magnifies and lengthens a transient v 0.1 m f 100 m h 0.05 0 10 m s 340 v voltage sensitive circuit 0 + 700 700 time ( m s) 020 10 di dt non-inductive resistor the snubber resistor limits the capacitor discharge current and reduces di dt stress. high di dt destroys the thyristor even though the pulse duration is very short. the rate of current rise is directly proportional to circuit voltage and inversely proportional to series inductance. the snubber is often the major offender because of its low inductance and close proximity to the thyristor. with no transient suppressor, breakdown of the thyristor sets the maximum voltage on the capacitor. it is possible to exceed the highest rated voltage in the device series because high voltage devices are often used to supply low voltage specifications. the minimum value of the snubber resistor depends on the type of thyristor, triggering quadrants, gate current amplitude, voltage, repetitive or non-repetitive operation, and required life expectancy. there is no simple way to pre- dict the rate of current rise because it depends on turn-on speed of the thyristor, circuit layout, type and size of snub- ber capacitor, and inductance in the snubber resistor. the equations in appendix d describe the circuit. however, the values required for the model are not easily obtained except by testing. therefore, reliability should be verified in the actual application circuit. table 1 shows suggested minimum resistor values esti- mated (appendix a) by testing a 20 piece sample from the four different triac die sizes. table 1. minimum non-inductive snubber resistor for four quadrant triggering. triac type peak v c volts r s ohms di dt a/ m s non-sensitive gate (i gt 10 ma) 8 to 40 a (rms) 200 300 400 600 800 3.3 6.8 11 39 51 170 250 308 400 400 reducing di dt triac di dt can be improved by avoiding quadrant 4 triggering. most optocoupler circuits operate the triac in quadrants 1 and 3. integrated circuit drivers use quadrants 2 and 3. zero crossing trigger devices are helpful because they prohibit triggering when the voltage is high. driving the gate with a high amplitude fast rise pulse increases di dt capability. the gate ratings section defines the maximum allowed current. inductance in series with the snubber capacitor reduces di dt . it should not be more than five percent of the load inductance to prevent degradation of the snubber's dv dt suppression capability. wirewound snubber resistors sometimes serve this purpose. alternatively, a separate inductor can be added in series with the snubber capacitor. it can be small because it does not need to carry the load current. for example, 18 turns of awg no. 20 wire on a t50-3 (1/2 inch) powdered iron core creates a non-saturat- ing 6.0 m h inductor. a 10 ohm, 0.33 m f snubber charged to 650 volts resulted in a 1000 a/ m s di dt . replacement of the non-inductive snub- ber resistor with a 20 watt wirewound unit lowered the rate of rise to a non-destructive 170 a/ m s at 800 v. the inductor gave an 80 a/ m s rise at 800 v with the noninductive resistor. the snubber capacitor a damping factor of 0.3 minimizes the size of the snub- ber capacitor for a given value of dv dt . this reduces the cost and physical dimensions of the capacitor. however, it raises voltage causing a counter balancing cost increase. snubber operation relies on the charging of the snubber capacitor. turn-off snubbers need a minimum conduction angle long enough to discharge the capacitor. it should be at least several time constants (r s c s ).
an1048/d http://onsemi.com 8 stored energy inductive switching transients e 1 2 li 0 2 watt-seconds or joules i 0 = current in amperes flowing in the inductor at t = 0. resonant charging cannot boost the supply voltage at turn-off by more than 2. if there is an initial current flowing in the load inductance at turn-off, much higher voltages are possible. energy storage is negligible when a triac turns off because of its low holding or recovery current. the presence of an additional switch such as a relay, ther- mostat or breaker allows the interruption of load current and the generation of high spike voltages at switch opening. the energy in the inductance transfers into the circuit capacitance and determines the peak voltage (figure 15). dv dt i c v pk i l c figure 6.15. interrupting inductive load current v pk c l i fast slow (b.) unprotected circuit (a.) protected circuit optional r capacitor discharge the energy stored in the snubber capacitor e c 1 2 cv 2 transfers to the snubber resistor and thyristor every time it turns on. the power loss is propor- tional to frequency (p av = 120 e c @ 60 hz). current diversion the current flowing in the load inductor cannot change instantly. this current diverts through the snubber resistor causing a spike of theoretically infinite dv dt with magnitude equal to (i rrm r) or (i h r). load phase angle highly inductive loads cause increased voltage and dv dt c at turn-off. however, they help to protect the thyristor from transients and dv dt s . the load serves as the snubber inductor and limits the rate of inrush current if the device does turn on. resistance in the load lowers dv dt and v pk (figure 16). dv dt m = 0.25 m = 0.5 m = 0.75 v pk 1.3 e 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1 0.9 1 1.1 1.2 1.4 1.5 1.6 1.7 1.4 1.2 1 0.8 0.6 2.2 2.1 2 1.9 1.8 damping factor m = 0 m = r s / (r l + r s ) m = 1 dv dt ( ) 0 normalized dv dt m resistive division ratio r s r l r s i rrm 0 figure 6.16. 0 to 63% dv dt / (e w ) normalized peak voltage v /e pk characteristic voltage waves damping factor and reverse recovery current determine the shape of the voltage wave. it is not exponential when the snubber damping factor is less than 0.5 (figure 17) or when significant recovery currents are present. v (volts) mt 2-1 0 63% dv dt s 100 v s, e 250 v, r l 0, i rrm 0 figure 6.17. voltage waves for different damping factors r = 0 1 time ( m s) 0.3 0.1 0 r = 0.1 r = 0.3 r = 1 3.5 2.8 2.1 4.2 4.9 5.6 6.3 0.7 0 100 200 300 400 500 1.4 7 0
an1048/d http://onsemi.com 9 normalized peak voltage and dv dt (r l 0, m 1, i rrm 0 ) normalized dv dt dv dt e 0 normalized v pk v pk e figure 6.18. trade-off between v pk and dv dt damping factor ( r ) 0 063% e 1 1063 % 0.8 0.6 0.4 0.2 1.2 1.8 1.4 1.6 2 2.8 2.6 2.4 2.2 1.8 1.6 1.4 2 1 1.2 0.8 0.6 0.4 0.2 0 dv dt dv dt o v pk dv dt 1063% dv dt max a variety of wave parameters (figure 18) describe dv dt some are easy to solve for and assist understanding. these include the initial dv dt , the maximum instantaneous dv dt , and the average dv dt to the peak reapplied voltage. the 0 to 63% dv dt s and 10 to 63% dv dt c definitions on device data sheets are easy to measure but difficult to compute. non-ideal behaviors core losses the magnetic core materials in typical 60 hz loads introduce losses at the snubber natural frequency. they appear as a resistance in series with the load inductance and winding dc resistance (figure 19). this causes actual dv dt to be less than the theoretical value. figure 6.19. inductor model lr c l depends on current amplitude, core saturation r includes core loss, winding r. increases with frequency c winding capacitance. depends on insulation, wire size, geometry complex loads many real-world inductances are non-linear. their core materials are not gapped causing inductance to vary with current amplitude. small signal measurements poorly char- acterize them. for modeling purposes, it is best to measure them in the actual application. complex load circuits should be checked for transient voltages and currents at turn-on and off. with a capacitive load, turn-on at peak input voltage causes the maximum surge current. motor starting current runs 4 to 6 times the steady state value. generator action can boost voltages above the line value. incandescent lamps have cold start currents 10 to 20 times the steady state value. transformers generate voltage spikes when they are energized. power factor correction circuits and switching devices create complex loads. in most cases, the simple crl model allows an approximate snubber design. however, there is no substitute for testing and measuring the worst case load conditions. surge currents in inductive circuits inductive loads with long l/r time constants cause asymmetric multi-cycle surges at start up (figure 20). trig- gering at zero voltage crossing is the worst case condition. the surge can be eliminated by triggering at the zero cur- rent crossing angle. i (amperes) figure 6.20. start-up surge for inductive circuit 240 vac 20 mhy i 0.1 w time (milliseconds) 40 zero voltage triggering, i rms = 30 a 0 90 80 160 120 200 core remanence and saturation cause surge currents. they depend on trigger angle, line impedance, core charac- teristics, and direction of the residual magnetization. for example, a 2.8 kva 120 v 1:1 transformer with a 1.0 ampere load produced 160 ampere currents at start-up. soft starting the circuit at a small conduction angle reduces this current. transformer cores are usually not gapped and saturate easily. a small asymmetry in the conduction angle causes magnetic saturation and multi-cycle current surges.
an1048/d http://onsemi.com 10 steps to achieve reliable operation include: 1. supply sufficient trigger current amplitude. triacs have different trigger currents depending on their quadrant of operation. marginal gate current or optocoupler led current causes halfwave operation. 2. supply sufficient gate current duration to achieve latching. inductive loads slow down the main terminal current rise. the gate current must remain above the specified i gt until the main terminal current exceeds the latching value. both a resistive bleeder around the load and the snubber discharge current help latching. 3. use a snubber to prevent triac dv dt c failure. 4. minimize designed-in trigger asymmetry. triggering must be correct every half-cycle including the first. use a storage scope to investigate circuit behavior during the first few cycles of turn-on. alternatively, get the gate circuit up and running before energizing the load. 5. derive the trigger synchronization from the line instead of the triac main terminal voltage. this avoids regenerative interaction between the core hysteresis and the triggering angle preventing trigger runaway, halfwave operation, and core saturation. 6. avoid high surge currents at start-up. use a current probe to determine surge amplitude. use a soft start circuit to reduce inrush current. distributed winding capacitance there are small capacitances between the turns and lay- ers of a coil. lumped together, they model as a single shunt capacitance. the load inductor behaves like a capacitor at frequencies above its self-resonance. it becomes ineffective in controlling dv dt and v pk when a fast transient such as that resulting from the closing of a switch occurs. this problem can be solved by adding a small snubber across the line. self-capacitance a thyristor has self-capacitance which limits dv dt when the load inductance is large. large load inductances, high power factors, and low voltages may allow snubberless operation. snubber examples without inductance power triac example figure 21 shows a transient voltage applied to a triac controlling a resistive load. theoretically there will be an instantaneous step of voltage across the triac. the only elements slowing this rate are the inductance of the wiring and the self-capacitance of the thyristor. there is an expo- nential capacitor charging component added along with a decaying component because of the ir drop in the snubber resistor. the non-inductive snubber circuit is useful when the load resistance is much larger than the snubber resistor. e (t o ) e r s r s r l e t (1 e t ) figure 6.21. non-inductive snubber circuit v step e r s r s r l resistor component time t = 0 e e t = (r l + r s ) c s e c s r s r l e capacitor component opto-triac examples single snubber, time constant design figure 22 illustrates the use of the rc time constant design method. the optocoupler sees only the voltage across the snubber capacitor. the resistor r1 supplies the trigger current of the power triac. a worst case design procedure assumes that the voltage across the power triac changes instantly. the capacitor voltage rises to 63% of the maximum in one time constant. then: r 1 c s 0.63 e dv dt s where dv dt s is the rated static dv dt for the optocoupler. design dv dt (0.63) (170) (2400) (0.1 f) 0.45 v s f cntl moc 3021 10 v/ m s time 240 m s 0.63 (170) l = 318 mhy 1 a, 60 hz r in v cc c1 0.1 m f 170 v 6 2.4 k 180 1 2n6073a 1 v/ m s 4 2 dv dt (v s) power triac optocoupler 0.99 0.35 figure 6.22. single snubber for sensitive gate triac and phase controllable optocoupler ( r = 0.67)
an1048/d http://onsemi.com 11 the optocoupler conducts current only long enough to trigger the power device. when it turns on, the voltage between mt2 and the gate drops below the forward thresh- old voltage of the opto-triac causing turn-off. the opto- coupler sees dv dt s when the power triac turns off later in the conduction cycle at zero current crossing. therefore, it is not necessary to design for the lower optocoupler dv dt c rating. in this example, a single snubber designed for the optocoupler protects both devices. figure 6.23. anti-parallel scr driver (50 v/ m s snubber, r = 1.0) 120 v 400 hz 1 mhy mcr2654 430 100 mcr2654 1n4001 0.022 m f 1 51 1n4001 100 v cc 6 5 4 3 2 moc3031 optocouplers with scrs anti-parallel scr circuits result in the same dv dt across the optocoupler and scr (figure 23). phase controllable opto-couplers require the scrs to be snubbed to their lower dv dt rating. anti-parallel scr circuits are free from the charge storage behaviors that reduce the turn-off capability of triacs. each scr conducts for a half-cycle and has the next half cycle of the ac line in which to recover. the turn- off dv dt of the conducting scr becomes a static forward blocking dv dt for the other device. use the scr data sheet dv dt s rating in the snubber design. a scr used inside a rectifier bridge to control an ac load will not have a half cycle in which to recover. the available time decreases with increasing line voltage. this makes the circuit less attractive. inductive transients can be sup- pressed by a snubber at the input to the bridge or across the scr. however, the time limitation still applies. opto dv dt c zero-crossing optocouplers can be used to switch inductive loads at currents less than 100 ma (figure 24). however a power triac along with the optocoupler should be used for higher load currents. l oa d cu rre nt (m a rms ) figure 6.24. moc 3062 inductive load current versus t a c s = 0.01 c s = 0.001 no snubber (r s = 100 w , v rms = 220 v, power factor = 0.5) t a , ambient temperature ( c) 0 20 80 70 60 50 40 30 20 10 100 90 80 30 40 50 60 70 a phase controllable optocoupler is recommended with a power device. when the load current is small, a mac97a triac is suitable. unusual circuit conditions sometimes lead to unwanted operation of an optocoupler in dv dt c mode. very large cur- rents in the power device cause increased voltages between mt2 and the gate that hold the optocoupler on. use of a larger triac or other measures that limit inrush current solve this problem. very short conduction times leave residual charge in the optocoupler. a minimum conduction angle allows recovery before voltage reapplication. the snubber with inductance consider an overdamped snubber using a large capacitor whose voltage changes insignificantly during the time under consideration. the circuit reduces to an equivalent l/r series charging circuit. the current through the snubber resistor is: i v r 1 e t , and the voltage across the triac is: e ir s . the voltage wave across the triac has an exponential rise with maximum rate at t = 0. taking its derivative gives its value as: dv dt 0 vr s l .
an1048/d http://onsemi.com 12 highly overdamped snubber circuits are not practical designs. the example illustrates several properties: 1. the initial voltage appears completely across the circuit inductance. thus, it determines the rate of change of current through the snubber resistor and the initial dv dt . this result does not change when there is resistance in the load and holds true for all damping factors. 2. the snubber works because the inductor controls the rate of current change through the resistor and the rate of capacitor charging. snubber design cannot ignore the inductance. this approach suggests that the snubber capacitance is not important but that is only true for this hypothetical condition. the snubber resistor shunts the thyristor causing unacceptable leakage when the capacitor is not present. if the power loss is tolerable, dv dt can be controlled without the capacitor. an example is the soft-start circuit used to limit inrush current in switching power supplies (figure 25). figure 6.25. surge current limiting for a switching power supply dv dt er s l snubber l g r s e snubber with no c e c1 ac line rectifier bridge snubber l ac line rectifier bridge c1 g r s triac design procedure dv dt c 1. refer to figure 18 and select a particular damping factor ( r ) giving a suitable trade-off between v pk and dv dt . determine the normalized dv dt corresponding to the chosen damping factor. the voltage e depends on the load phase angle: e 2 v rms sin ( ) where tan 1 x l r l where f = measured phase angle between line v and load i r l = measured dc resistance of the load. then z v rms i rms r l 2 x l 2 x l z 2 r l 2 and l x l 2 f line . if only the load current is known, assume a pure inductance. this gives a conservative design. then: l v rms 2 f line i rms where e 2 v rms . for example: e 2 120 170 v; l 120 (8 a) (377 rps) 39.8 mh. read from the graph at r = 0.6, v pk = (1.25) 170 = 213 v. use 400 v triac. read dv dt ( r 0.6) 1.0. 2. apply the resonance criterion: 0 spec dv dt dv dt (p) e . 0 5 10 6 v s (1) (170 v) 29.4 10 3 rps. c 1 0 2 l 0.029 f 3. apply the damping criterion: r s 2 r l c 2 (0.6) 39.8 10 3 0.029 10 6 1400 ohms. dv dt c safe area curve figure 26 shows a mac15 triac turn-off safe operating area curve. turn-off occurs without problem under the curve. the region is bounded by static dv dt at low values of di dt c and delay time at high currents. reduction of the peak current permits operation at higher line frequency. this triac operated at f = 400 hz, t j = 125 c, and i tm = 6.0 amperes using a 30 ohm and 0.068 m f snubber. low damping factors extend operation to higher di dt c , but capacitor sizes increase. the addition of a small, saturable commutation inductor extends the allowed current rate by introducing recovery delay time.
an1048/d http://onsemi.com 13 dv dt ( ) (v/ s) m c di dt c amperes millisecond figure 6.26. versus t j = 125 c dv dt c di dt c 100 10 0.1 50 10 1 with commutation l 30 14 18 22 26 34 38 42 46 itm = 15 a di dt c 6fitm 10 3 a ms mac 16-8, commutational l 33 turns # 18, 52000-1a tape wound core 3 4 inch od static dv dt design there is usually some inductance in the ac main and power wiring. the inductance may be more than 100 m h if there is a transformer in the circuit or nearly zero when a shunt power factor correction capacitor is present. usually the line inductance is roughly several m h. the minimum inductance must be known or defined by adding a series inductor to insure reliable operation (figure 27). figure 6.27. snubbing for a resistive load 50 v/ m s 0.33 m f 10 l s 1 100 m h 20 a 340 v 12 w heater one hundred m h is a suggested value for starting the design. plug the assumed inductance into the equation for c. larger values of inductance result in higher snubber resistance and reduced di dt . for example: given e = 240 2 340 v. pick r = 0.3. then from figure 18, v pk = 1.42 (340) = 483 v. thus, it will be necessary to use a 600 v device. using the previously stated formulas for w 0 , c and r we find: 0 50 10 6 v s (0.73) (340 v) 201450 rps c 1 (201450) 2 (100 10 6 ) 0.2464 f r 2 (0.3) 100 10 6 0.2464 10 6 12 ohms variable loads the snubber should be designed for the smallest load inductance because dv dt will then be highest because of its dependence on w 0 . this requires a higher voltage device for operation with the largest inductance because of the corre- sponding low damping factor. figure 28 describes dv dt for an 8.0 ampere load at various power factors. the minimum inductance is a component added to prevent static dv dt firing with a resistive load. l r mac 218a6fp 8 a load 68 w 120 v 60 hz 0.033 m f dv dt s 100 v s dv dt c 5v s r r l v step v pk dv dt r w mhy v v v/ m s 0.75 15 0.1 170 191 86 0.03 0 39.8 170 325 4.0 0.04 10.6 28.1 120 225 3.3 0.06 13.5 17.3 74 136 2.6 figure 6.28. snubber for a variable load
an1048/d http://onsemi.com 14 examples of snubber designs table 2 describes snubber rc values for dv dt s . figures 31 and 32 show possible r and c values for a 5.0 v/ m s dv dt c assuming a pure inductive load. table 2. static designs (e = 340 v, v peak = 500 v, r = 0.3) dv dt 5.0 v/ m s 50 v/ m s 100 v/ m s l m h c m f r ohm c m f r ohm c m f r ohm 47 0.15 10 100 0.33 10 0.1 20 220 0.15 22 0.033 47 500 0.068 51 0.015 110 1000 3.0 11 0.033 100 transient and noise suppression transients arise internally from normal circuit operation or externally from the environment. the latter is partic- ularly frustrating because the transient characteristics are undefined. a statistical description applies. greater or smaller stresses are possible. long duration high voltage transients are much less probable than those of lower amplitude and higher frequency. environments with infre- quent lightning and load switching see transient voltages below 3.0 kv. figure 6.29. snubber resistor for = 5.0 v/ m s dv dt c r ( o hms ) s 80 a 40 a 20 a 0 0.6 a rms 2.5 a 5 a damping factor 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 10k 100 1000 10 10 a pure inductive load, v 120 v rms , i rrm 0 figure 6.30. snubber capacitor for = 5.0 v/ m s dv dt c c ( f) s m 0.001 2.5 a 0.01 0.6 a 5 a 10 a 20 a 1 0.1 80 a rms 40 a 0 damping factor 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 pure inductive load, v 120 v rms , i rrm 0 the natural frequencies and impedances of indoor ac wiring result in damped oscillatory surges with typical fre- quencies ranging from 30 khz to 1.5 mhz. surge ampli- tude depends on both the wiring and the source of surge energy. disturbances tend to die out at locations far away from the source. spark-over (6.0 kv in indoor ac wiring) sets the maximum voltage when transient suppressors are not present. transients closer to the service entrance or in heavy wiring have higher amplitudes, longer durations, and more damping because of the lower inductance at those locations. the simple crl snubber is a low pass filter attenuating frequencies above its natural resonance. a steady state sinusoidal input voltage results in a sine wave output at the same frequency. with no snubber resistor, the rate of roll off approaches 12 db per octave. the corner frequency is at the snubber's natural resonance. if the damping factor is low, the response peaks at this frequency. the snubber resistor degrades filter characteristics introducing an up-turn at w = 1 / (rc). the roll-off approaches 6.0 db/octave at frequencies above this. inductance in the snubber resistor further reduces the roll-off rate. figure 32 describes the frequency response of the circuit in figure 27. figure 31 gives the theoretical response to a 3.0 kv 100 khz ring-wave. the snubber reduces the peak voltage across the thyristor. however, the fast rise input causes a high dv dt step when series inductance is added to the snubber resistor. limiting the input voltage with a transient suppressor reduces the step.
an1048/d http://onsemi.com 15 figure 6.31. theoretical response of figure 33 circuit to 3.0 kv ieee 587 ring wave (r sc = 27.5 w ) v ( vo l t s ) mt 2-1 400 with 5 m hy 450 v mov at ac input with 5 m hy and without 5 m hy 6 5 4 2 1 0 time ( m s) 3 400 0 figure 6.32. snubber frequency response v out v in vo l tag e gain ( db) frequency (hz) 10k with 5 m hy without 5 m hy 40 0.33 m f 10 5 m h 12 v in 100 m h 1m +10 0 100k 30 20 10 v out the noise induced into a circuit is proportional to dv dt when coupling is by stray capacitance, and di dt when the coupling is by mutual inductance. best suppression requires the use of a voltage limiting device along with a rate limiting crl snubber. the thyristor is best protected by preventing turn-on from dv dt or breakover. the circuit should be designed for what can happen instead of what normally occurs. in figure 30, a mov connected across the line protects many parallel circuit branches and their loads. the mov defines the maximum input voltage and di dt through the load. with the snubber, it sets the maximum dv dt and peak voltage across the thyristor. the mov must be large because there is little surge limiting impedance to prevent its burn-out. in figure 32, there is a separate suppressor across each thyristor. the load impedance limits the surge energy deliv- ered from the line. this allows the use of a smaller device but omits load protection. this arrangement protects each thyristor when its load is a possible transient source. figure 6.33. limiting line voltage v max figure 6.34. limiting thyristor voltage it is desirable to place the suppression device directly across the source of transient energy to prevent the induc- tion of energy into other circuits. however, there is no protection for energy injected between the load and its con- trolling thyristor. placing the suppressor directly across each thyristor positively limits maximum voltage and snub- ber discharge di dt . examples of snubber applications in figure 35, triacs switch a 3 phase motor on and off and reverse its rotation. each triac pair functions as a spdt switch. the turn-on of one triac applies the differ- ential voltage between line phases across the blocking device without the benefit of the motor impedance to constrain the rate of voltage rise. the inductors are added to prevent static dv dt firing and a line-to-line short.
an1048/d http://onsemi.com 16 figure 6.35. 3 phase reversing motor moc 3081 snubber all mov's are 275 v rms all triacs are mac218a10fp 0.15 m f 22 w 2 w wirewound 43 4 6 g 1 2 91 1/3 hp 208 v 3 phase 100 m h rev f 1 91 g 1 2 300 6 fwd 4 snubber n f 2 f 3 moc 3081 91 g 1 2 300 6 4 snubber moc 3081 91 g 1 2 300 6 4 snubber moc 3081 91 g 1 2 300 4 6 snubber rev fwd 100 m h moc 3081 snubber
an1048/d http://onsemi.com 17 figure 36 shows a split phase capacitor-run motor with reversing accomplished by switching the capacitor in series with one or the other winding. the forward and reverse triacs function as a spdt switch. reversing the motor applies the voltage on the capacitor abruptly across the blocking thyristor. again, the inductor l is added to prevent dv dt s firing of the blocking triac. if turn-on occurs, the forward and reverse triacs short the capacitors (c s ) resulting in damage to them. it is wise to add the resistor r s to limit the discharge current. figure 6.36. split phase reversing motor 5.6 3.75 330 v motor 1/70 hp 0.26 a 2n6073 115 500 m h l s rev 46 v/ m s max fwd 0.1 91 c s 0.1 r s 91 figure 37 shows a a tap changer.o this circuit allows the operation of switching power supplies from a 120 or 240 vac line. when the triac is on, the circuit functions as a conventional voltage doubler with diodes d1 and d2 con- ducting on alternate half-cycles. in this mode of operation, inrush current and di dt are hazards to triac reliability. series impedance is necessary to prevent damage to the triac. the triac is off when the circuit is not doubling. in this state, the triac sees the difference between the line volt- age and the voltage at the intersection of c1 and c2. tran- sients on the line cause dv dt s firing of the triac. high inrush current, di dt , and overvoltage damage to the filter capacitor are possibilities. prevention requires the addition of a rc snubber across the triac and an inductor in series with the line. thyristor types sensitive gate thyristors are easy to turn-on because of their low trigger current requirements. however, they have less dv dt capability than similar non-sensitive devices. a non-sensitive thyristor should be used for high dv dt . triac commutating dv dt ratings are 5 to 20 times less than static dv dt ratings. figure 6.37. tap changer for dual voltage switching power supply c 1 + r l 0 g c s r s 120 v 240 v snubber inductor 120 vac or 240 vac d 1 d 2 d 4 d 3 c 2 + phase controllable optocouplers have lower dv dt ratings than zero crossing optocouplers and power triacs. these should be used when a dc voltage component is present, or to prevent turn-on delay. zero crossing optocouplers have more dv dt capability than power thyristors; and they should be used in place of phase controllable devices in static switching applications. appendix a measuring dv dt s figure 38 shows a test circuit for measuring the static dv dt of power thyristors. a 1000 volt fet switch insures that the voltage across the device under test (d.u.t.) rises rapidly from zero. a differential preamp allows the use of a n-channel device while keeping the storage scope chassis at ground for safety purposes. the rate of voltage rise is adjusted by a variable rc time constant. the charging resistance is low to avoid waveform distortion because of the thyristor's self-capacitance but is large enough to pre- vent damage to the d.u.t. from turn-on di dt . mounting the miniature range switches, capacitors, and g-k network close to the device under test reduces stray inductance and allows testing at more than 10 kv/ m s.
an1048/d http://onsemi.com 18 figure 6.38. circuit for static measurement of power thyristors dv d t x100 probe x100 probe differential preamp mount dut on temperature controlled c m plate dut 2 1 g r gk 2 w 20 k v drm /v rrm select 2 w 27 0.33 1000 v 0.047 1000 v 1000 10 watt wirewound 1000 1/4 w 56 2 w vernier 82 2 w 100 2 w 470 pf 0.001 0.005 0.01 0.047 0.1 0.47 1.2 meg 2 w each 1 meg power 2 w test mtp1n100 all components are non-inductive unless otherwise shown 01000 v 10 ma 1n967a 18 v 1n914 f = 10 hz pw = 100 m s 50 w pulse generator 20 v dv dt appendix b measuring dv dt c a test fixture to measure commutating dv dt is shown in figure 39. it is a capacitor discharge circuit with the load series resonant. the single pulse test aids temperature con- trol and allows the use of lower power components. the limited energy in the load capacitor reduces burn and shock hazards. the conventional load and snubber circuit pro- vides recovery and damping behaviors like those in the application. the voltage across the load capacitor triggers the d.u.t. it terminates the gate current when the load capacitor volt- age crosses zero and the triac current is at its peak. each v drm , i tm combination requires different compo- nents. calculate their values using the equations given in figure 39. commercial chokes simplify the construction of the nec- essary inductors. their inductance should be adjusted by increasing the air gap in the core. removal of the magnetic pole piece reduces inductance by 4 to 6 but extends the cur- rent without saturation. the load capacitor consists of a parallel bank of 1500 vdc non-polar units, with individual bleeders mounted at each capacitor for safety purposes. an optional adjustable voltage clamp prevents triac breakdown. to measure dv dt c , synchronize the storage scope on the current waveform and verify the proper current amplitude and period. increase the initial voltage on the capacitor to compensate for losses within the coil if necessary. adjust the snubber until the device fails to turn off after the first half-cycle. inspect the rate of voltage rise at the fastest passing condition.
an1048/d http://onsemi.com 19 + + 2 w 51 + 5 c s 2n3904 0.1 2.2 k 1/2 sync triac under test 56 2 watt case controlled heatsink 0.1 2n3906 5 g 1 2 pearson 301 x 2n3904 1/2 w 120 2n3906 120 1/2 w 2n390 6 2n3904 r s 1/2 w + 0.22 270 k 1n5343 7.5 v 0.22 q 1 q 3 2n3906 2n3904 1/2 w 360 1 k 5 + 5 non-inductive resistor decade 010 k, 1 w step 2 w 51 k 51 k 2 w hg = w at low ld10-1000-1000 + clamp mr760 clamp 62 m f 1 kv l l 6.2 meg 2 w 150 k 910 k 2 w 2 w 910 k r l q 3 q 1 70 ma 1.5 kv triad c30x 50 h, 3500 w 2 w 51 6.2 meg 2 w 360 1 k 270 k 2n3904 2n390 6 q 3 q 1 0-1 kv 20 ma c (non-polar) l mr760 mr760 2.2 m 2.2 m 2.2 m, 2w 2.2 m, 2w 2.2 m 2.2 m 0.01 figure 6.39. test circuit for power triacs dv dt c m c l i pk w 0 v ci i p t 2 v ci l l v ci w 0 i pk t 2 4 2 c l w 0 i l l di dt c 6f i pk 10 6 a s dv dt capacitor decade 110 f, 0.011 f, 100 pf 0.01 f m m 0.01
an1048/d http://onsemi.com 20 appendix c dv dt derivations definitions 1.0 r t r l r s total resistance 1.1 m r s r t snubber divider ratio 1.2 0 1 lc s undamped natural frequency damped natural frequency 1.3 r t 2l wave decrement factor 1.4 c 2 1 2li 2 1 2cv 2 initial energy in inductor final energy in capacitor 1.5 c i e l c initial current factor 1.6 r r t 2 c l 0 damping factor 1.7 v 0 l e r s i initial voltage drop at t 0 across the load 1.8 i c s er l l dv dt
0 initial instantaneous dv dt at t 0, ignoring any initial instantaneous voltage step at t 0 because of i rrm 1.9 dv dt
0 v ol r t l . for all damping condition s 2.0 when i 0, dv dt
0 er s l dv dt
max maximum instantaneous dv dt t max time of maximum instantaneous dv dt t peak time of maximum instantaneous peak voltage across thyristor average dv dt v pk t pk slope of the secant line from t 0 through v pk v pk maximum instantaneous voltage across the thyristor. constants (depending on the damping factor): 2.1 no damping ( r 0) 0 r t r 0 2.2 underdamped (0 r 1) 0 2 2 0 1 r 2 2.3 critical damped ( r 1) 0, 0, r 2 l c ,c 2 r t 2.4 overdamped ( r 1) 2 0 2 0 r 2 1 laplace transforms for the current and voltage in figure 40 are: 3.0 i (s) e l si s 2 s r t l 1 lc ;e e s sv 0 l s 2 r t l s 1 lc initial conditions i i rrm v c s 0 figure 6.40. equivalent circuit for load and snubber t = 0 i r l l c s r s e the inverse laplace transform for each of the conditions gives: underdamped (typical snubber design) 4.0 e e v 0 l cos ( t) sin ( t) e t sin ( t) e t 4.1 de dt v 0 l 2 cos ( t) ( 2 2 ) sin ( t) e t cos ( t) sin ( t) e t 4.2 t pk 1 tan 1 2 v 0 l v 0 l 2 2
when m 0, r s 0, i 0: t pk
an1048/d http://onsemi.com 21 4.3 v pk e 0 t pk 0 2 v 0 l 2 2 v 0 l
when i 0, r l 0, m 1: 4.4 v pk e (1 e t pk ) average dv dt v pk t pk 4.5 t max 1 atn (2 v 0 l ( 2 3 2 )) v 0 l ( 3 3 2 ) ( 2 2 ) 4.6 dv dt max v 0 l 2 0 2 2 v 0 l 2
e t max no damping 5.0 e e(1 cos ( 0 t)) i c 0 sin ( 0 t) 5.1 de dt e 0 sin ( 0 t) i c cos ( 0 t) 5.2 dv dt 0 i c 0 when i 0 5.3 t pk tan 1 i ce 0 0 5.4 v pk e e 2 i 2 0 2 c 2
5.5 dv dt avg v pk t pk 5.6 t max 1 0 tan 1 0 ec i 1 0 2 when i 0 5.7 dv dt max i c e 2 0 2 c 2 i 2
0 e when i 0 critical damping 6.0 e e v 0 l (1 t)e t te t 6.1 de dt v o l (2 t) (1 t) e t 6.2 t pk 2 2v 0l v 0 l 6.3 v pk e v 0 l (1 t pk ) t pk e t pk 6.4 average dv dt v pk t pk when i 0, r s 0, m 0 e(t) rises asymptotically to e. t pk and average d v dt do not exist. 6.5 t max 3 v 0 l 2 2 v 0 l when i 0, t max 0 for r s r t 3 4, then dv dt max dv dt 0 6.6 dv dt max v 0 l (2 t max ) (1 t max ) e t max appendix d snubber discharge di dt derivations overdamped 1.0 i v c s l s t sinh ( t) 1.1 i pk v c s c s l s
e t pk 1.2 t pk 1 tanh 1 critical damped 2.0 i v c s l s te t 2.1 i pk 0.736 v c s r s 2.2 t pk 1
an1048/d http://onsemi.com 22 underdamped 3.0 i v c s l s e t sin ( t) 3.1 i pk v c s c s l s e t pk 3.2 t pk 1 tan 1 figure 6.41. equivalent circuit for snubber discharge l s r s c s v c s i t = 0 initial conditions : i 0, v c s initial voltage no damping 4.0 i v c s l s sin ( t) 4.1 i pk v c s c s l s 4.2 t pk 2 bibliography bird, b. m. and k. g. king. an introduction to power electronics . john wiley & sons, 1983, pp. 250281. blicher, adolph. thyristor physics . springer-verlag, 1976. gempe, horst. aapplications of zero voltage crossing optically isolated triac drivers,o an982, motorola inc., 1987. aguide for surge withstand capability (swc) tests,o ansi 337.90a-1974, ieee std 4721974. aieee guide for surge voltages in low-voltage ac power circuits,o ansi/ieee c62.41-1980, ieee std 5871980. ikeda, shigeru and tsuneo araki. a the di dt capability of thyristors,o proceedings of the ieee, vol. 53, no. 8, august 1967. kervin, doug. a the moc3011 and moc3021,o eb-101, motorola inc., 1982. mcmurray, william. aoptimum snubbers for power semiconductors,o ieee transactions on industry applica- tions, vol. ia-8, september/october 1972. rice, l. r. a why r-c networks and which one for your converter,o westinghouse tech tips 5-2. asaturable reactor for increasing turn-on switching capability,o scr manual sixth edition, general electric, 1979. zell, h. p. adesign chart for capacitor-discharge pulse circuits,o edn magazine, june 10, 1968.
an1048/d http://onsemi.com 23 notes
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